1. Technical Field
Various embodiments of the present invention relate to a semiconductor apparatuses. In particular, certain embodiments relate to a three-dimensional (3D) semiconductor apparatus including a plurality of chips stacked therein.
2. Related Art
In an effort to increase the degree of integration of a semiconductor apparatus, there has been developed a three-dimensional semiconductor apparatus in which a plurality of chips are stacked and packaged. Because two or more chips are stacked therein, the 3D semiconductor apparatus can achieve a maximum degree of integration in the same space.
Various schemes exist to implement the three-dimensional semiconductor apparatus. Among them, a scheme exists in which a plurality of chips with the same structure are stacked and the stacked chips are coupled to one another using wires such as metal lines, so that they operate as a single semiconductor apparatus.
Also, recently, a TSV (through-silicon via) type semiconductor apparatus has been disclosed in the art, in which silicon vias are formed through a plurality of stacked chips so that all the chips are electrically connected to one another. Since the chips are electrically connected to one another through the silicon vias vertically passing through the chips in the TSV type semiconductor apparatus, it is possible to efficiently reduce the size of a package, as compared with a semiconductor apparatus in which respective chips are electrically connected to one another through bonding wirings provided around the edges of the chips. However, the TSV connections require through holes in the chips, a layout margin of a chip is reduced as the number of the TSVs is increased.
FIG. 1 is a diagram schematically illustrating a typical configuration of a semiconductor apparatus. In FIG. 1, a semiconductor apparatus 10 has a structure in which two chips Master and Slave are electrically connected to each other through TSVs 11. In general, since a three-dimensional semiconductor apparatus communicates with other apparatuses through a chip operating as a master chip, the second chip Slave transmits data stored in a memory cell block 12 through the TSVs 11, and the data is output to a pad 15 through a read control unit 13 of the first chip Master. The second chip Slave receives data through the pad 15 and a write control unit 14 of the first chip Master, and the TSVs 11, and stores the received data in the memory cell block 12. In this regard, the TSVs 11 electrically connect data input/output lines GIO1<0:n> of the first chip Master to data input/output lines GIO2<0:n> of the second chip Slave. However, in such a case, the number of the TSVs 11 increases because of the large number of the data input/output lines GIO1<0:n> and GIO2<0:n>. The semiconductor apparatus receives serial data, converts the serial data to parallel data, and stores the parallel data in a set of memory cells, or converts the parallel data to serial data and outputs the serial data through the pad. Therefore, the number of the data input/output lines for transmitting the parallel data, for example, may be 64, 128, 256 or more. As a consequence, the number of the TSVs for connecting the data input/output lines together also increases because of the large number of the data input/output lines. Due to the increased TSVs, it may be difficult to sufficiently ensure a chip fabrication area.
FIG. 2 is a diagram illustrating another typical configuration of a semiconductor apparatus. In FIG. 2, two chips Master and Slave constituting a semiconductor apparatus 20 are illustrated to have the same structure, unlike that of FIG. 1. That is, the semiconductor apparatus 20 has a configuration in which data input/output lines GIO1<0:n> and GIO2<0:n> are not electrically interconnected respectively through TSVs 21, but instead pads 22 and 23 are electrically connected to each other through the TSVs 21. Therefore, the number of the required TSVs 21 corresponds to the number of the pads 22 and 23. In general, since the number of the pads 22 and 23 is smaller than the number of the data input/output lines GIO1<0:n> and GIO2<0:n>, the semiconductor apparatus 20 requires a smaller number of TSVs as compared with the semiconductor apparatus 10 illustrated in FIG. 1. However, the configuration of the semiconductor apparatus 20 makes it very difficult to adjust the timing of the output data and the amount of current consumption increases. That is, since various data signals in each chip travel different lengths of paths, skew may occur at the output timing of the data. Furthermore, since the load seen from the TSVs 21 is very large, the consumed amount of current for driving data transmitted on the TSVs 21 may increase.